Architectures/ARM/Glossary

Glossary

This page will be used to document a list of terms and acronyms used in reference to the ARM Architecture

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

A

Aarch32

The ARMv8 32-bit execution state, that uses 32-bit general purpose registers, and a 32-bit program counter (PC), stack pointer (SP), and link register (LR). AArch32 execution state provides a choice of two instruction sets, A32 and T32. Operation in AArch32 state is compatible with ARMv7-A operation.

Aarch64

The ARMv8 64-bit execution state, that uses 64-bit general purpose registers, and a 64-bit program counter (PC), stack pointer (SP), and exception link registers (ELR). AArch64 execution state provides a single instruction set, A64..

Application Binary Interface for the ARM Architecture (ABI)

A collection of specifications, some open and some specific to the ARM architecture, that regulate the inter-operation of binary code in a range of execution environments for ARM processors. The base standard specifies those aspects of code generation that must conform to a standard that supports inter-operation. It is aimed at authors and vendors of C and C++ compilers, linkers, and runtime libraries.

B

Big-endian

In the context of the ARM architecture, big-endian is defined as the memory organization in which:

• a byte or halfword at a word-aligned address is the most significant byte or halfword at that address
• a byte at a halfword-aligned address is the most significant byte in the halfword at that address.

C

Coprocessor

D

Data Abort

An indication from a memory system to the processor of an attempt to access an illegal data memory location.