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= Status = | = Status = | ||
Status: The stage3 disk image boots to a shell, with coreutils <br> | Status: The stage3 disk image boots to a shell, with coreutils, binutils, util-linux. GCC is on the disk image but currently doesn't work. <br> | ||
Last updated: 2016-08- | Last updated: 2016-08-07 | ||
For the latest information, see: | For the latest information, see: | ||
Revision as of 20:59, 7 August 2016
RISC-V (pronounced "RISC Five") is an open source instruction set architecture (ISA). This project, informally called Fedora/RISC-V, aims to get Fedora bootstrapped on the RISC-V (64 bit) architecture.
Downloads
- http://copr-fe.cloud.fedoraproject.org/coprs/rjones/riscv/
- COPR repository (for Fedora 24/x86_64) containing: QEMU, Spike, cross-compiler toolchain
- http://git.annexia.org/?p=fedora-riscv.git
- Git repository containing the bootstrapping work. Read the README file!
- http://oirase.annexia.org/riscv/
- Interim stage3 disk image.
Status
Status: The stage3 disk image boots to a shell, with coreutils, binutils, util-linux. GCC is on the disk image but currently doesn't work.
Last updated: 2016-08-07
For the latest information, see: http://git.annexia.org/?p=fedora-riscv.git;a=blob;f=README
Communications
There is no specific mailing list. Use Fedora devel for now.
On FreeNode IRC: #fedora-riscv